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mic2310 single-fet, constant power-limit hot swap controller micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com july 2008 m9999-070108-a general description the mic2310 is a single-channel, positive voltage, constant power-limit hot swap controller designed to provide for the safe insertion and removal of pc boards into fixed, rack, and pedestal mid- or back-planes using few external components. in addi tion, the mic2310 employs a patent-pending, output load power-limiting technique where the current limit is inversely proportional to the output load voltage, such that the power product will not exceed the programmed power limit any longer than the externally programmed primary overcurrent period. the mic2310 is ideally suited to address the power-limiting and timing requirements per the ul60950 specification for 240-va applications. the mic2310 incorporates high-side controller circuitry for an external n-channel mosfet for which the mosfet drain current rate of change is user- programmable via an external capacitor. the mic2310 employs dual-speed, dual-level overcurrent fault protection. the primary overcu rrent detector response time is programmable via an external current sense resistor and the secondary overcurrent detector is 2-bit user- programmable and exhibits a very fast (default) response to faults to ensure that t he system power supplies are protected against catastrophic load current and short- circuit faults. additionally, an analog output (voltage) signal is provided that is proportional to the steady-state load current to allow monitoring of the system?s power. a pwrgd signal is provided to indicate a valid output voltage that can be used to enable a dc-dc power module. data sheets and support doc umentation can be found on micrel?s web site at www.micrel.com. features ? provides safe pcb insertion and removal from live +12v backplanes ? patent-pending, adaptive ci rcuit breaker threshold control ? maintains constant power product at output ? power-limit product (va) is externally programmable for various power applications ? dual-level, dual-speed over current detection/protection ? programmable primary detector response time ? fast (< 1 s) secondary detector response time to short circuit conditions ? user-programmable threshold settings via (2) digital inputs ? steady-state load current monitoring ? programmable inrush current slew-rate control ? electronic circuit breaker functions after fault ? latch off ? automatic retry ? programmable input undervoltage lockout and overvoltage protection ? fault reporting: ? open-drain ?power-is-good? output ? open-drain ?i_flt? output signaling for all current faults ? shorted r sense and damaged mosfet detection (d-g and d-s shorts) applications ? ul60950, en60950, and c sa1950 systems (240-va) ? general power-limiting applications ? base stations ? enterprise servers ? high-reliability servers ? enterprise switch networks ? +12v backplanes
micrel, inc. mic2310 july 2008 2 m9999-070108-a typical application gate vreg sense cpgnd mic2310 s0 s1 enable vcc hw_flt agnd v out 12v@20a pw rgd cretry r sense 0.5% c1 1.5f power-good output v in 12v to system management controller q1 irl3713s d 2 pak c6 0.1f r1 r3 1% r5 1% disch c5 0.068f 23 22 10 21 3 8 7 11 34 12 vccsense c3 0.68f cprimary cslew source gndsense loadsense i_flt uvlo viss c4 0.47f 24 19 18 15 16 4 17 9 20121314 3 1 ovp 2 6 v logic overcurrent fault output hardware fault output s[1,0]=x,x q2 zumt618 sot-323 c2* c7 0.01f r2 c disch r9 r4 1% r8 r7 r6 * the value of c2 is flexible and dependant upon the parasitic inductance, which should be minimzed as much as possible. a inductance) for c2 is 56f, minimum c load
micrel, inc. mic2310 july 2008 3 m9999-070108-a ordering information part number pwrgd state i_flt state fault condition status package lead finish mic2310-1zts active-high active-high latched/auto-retry 24-pin tssop pb-free MIC2310-2ZTS active-low active-low latched/auto-retry 24-pin tssop pb-free note: 1. other voltage available. contact micrel for details. pin configuration agnd hw_flt 13 12 cslew pwrgd 14 11 1 uvlo ovp viss vreg nc enable s0 s1 cretry cprimary 24 vcc vccsense sense gate cpgnd source loadsense gndsense disch i_flt 23 22 21 20 19 18 17 16 15 2 3 4 5 6 7 8 9 10 agnd hw_flt 13 12 cslew /pwrgd 14 11 1 uvlo ovp viss vreg nc enable s0 s1 cretry cprimary 24 vcc vccsense sense gate cpgnd source loadsense gndsense disch /i_flt 23 22 21 20 19 18 17 16 15 2 3 4 5 6 7 8 9 10 24-pin tssop (ts) mic2310-1zts 24-pin tssop (ts) MIC2310-2ZTS
micrel, inc. mic2310 july 2008 4 m9999-070108-a pin description pin number pin name pin function 1 uvlo undervoltage lockout input. when the appli ed voltage at the uvlo pin is higher than the controller?s v uvloh threshold voltage, the gate drive circuits are active when enable= high. if the applied volta ge at the uvlo pin falls below the controller?s v uvlol threshold voltage, the gate dr ive circuits are disabled to turn the external mosfet off. in addition, t he disch circuit is activated to drive an optional, external discharge transistor alone (illustrated in the typical application circuit) or in combination with an scr for a very fast discharge circuit configuration. 2 ovp overvoltage protection input. when the ap plied voltage at the ovp pin is higher than the controller?s v ovph threshold voltage, the gate drive circuit is disabled to turn the external mosfet off. in addit ion, the disch circuit is activated to drive an optional, external discharge transistor alone (illustrated in the typical application circuit) or in combination with an scr for a very fast discharge circuit configuration. using an external resist or divider, the uvlo and the ovp pins form a window comparator that defines the supply voltage range within which the load may be safely powered. 3 viss steady-state output curre nt monitor. this output signal provides an analog voltage that is proportional to the st eady-state load current. this signal is provided as an input to the system supe rvisor/processor to monitor the dc current/power level of the application circuit. 4 vreg internal +5v regulator bypass. connect a 0.1-f, 16v ceramic capacitor from this pin to agnd. 5 nc no connection 6 enable enable input. an active asserted-high digital input that cont rols the operation of the mic2310. activated after the int ernal por timer has terminated, a low- to-high transition on this pin commences a start-up sequence if the applied v cc is above the v uvloh and below the v ovph threshold voltages. while enable = low, the gate pin is held to 0v and the disch output is activated. the enable input can be used to reset the internal circuit breaker by applying a high-to-low-to-high transition as defined by t enlpw following either a load current fault, an open loadsense fault, an open gndsense fault, or a shorted rsense fault. 7 s0 8 s1 secondary oc detector current thres hold digital inputs ? s1 is the msb and s0 is the lsb. when used together, s[1:0] sets the overcurrent threshold for the secondary overcurrent detection circuit to one of four levels relative to the primary overcurrent detector nominal thresh old. for example, s[1:0] = l, l sets the secondary overcurrent threshold at 1.3x ; s[1:0] = l, h sets a 1.5x threshold; s[1:0] = h, l sets a 2x threshold, and s[1: 0] = h, h sets a 1.75x threshold. if the s[1:0] pins are not connected or left nc, the default setting is s[1:0] = l, l or 1.3x. the permissible voltage range on these inputs is agnd s[1:0] v cc . 9 cretry auto-retry timing capacitor. a capacitor connected from the cretry pin to agnd configures the mic2310 to re-star t automatically with enable = high after the circuit breaker trips and latches off. it also sets the ?cool-off? time delay before a new load current start-up sequ ence is initiated. to configure the mic2310?s circuit breaker to latch off after fault, connect this pin to agnd. the circuit breaker latches off and remains latched off unless the enable input is toggled high-to-low-to-high as defined by t enlpw or the v cc supply voltage is turned off then on. 10 cprimary primary overcurrent detector timing capa citor. connecting a capacitor from the cprimary pin to agnd sets the respons e time of the controller?s primary overcurrent detection circuit to gate off in the event of an overcurrent condition. if the cprimary pin is not connected, the pr imary overcurrent detection response time defaults to t pocsense , typically 250s as specified in the electrical characteristics table. the c ontroller incorporates a patent-pending built-in test for a faulty cprimary capacitor.
micrel, inc. mic2310 july 2008 5 m9999-070108-a pin description (continued) pin number pin name pin function 11 cslew inrush current slew rate control input. to adjust the inrush load current profile (controlled di drain /dt), connect a capacitor from this pin to vcc. to adjust the mosfet gate voltage profile (controlled dv gate /dt), leave this pin open (floating) and connect a capacitor fr om gate to agnd. for additional information on the operation of this f unction, please refer to the functional description section. 12 agnd analog ground. connect this pin to the system analog ground plane. 13 hw_flt external mosfet hardware fault digital output. this output is an open-drain, active-high signal that should be connected to a +3.3v logic supply by a 10k ? resistor. this digital output is active a fter the internal por timer has terminated and becomes asserted (high) due to a fault under the following conditions: a) a shorted dg mosfet with enable = low; b) a shorted ds mosfet with enable = low; c) a shorted r sense ; d) a shorted ds mosfet after steady- state operation with enable = high-to-lo w; or e) a shorted dg or ds while en = high and disch = high; or f) a shorted c primary to agnd. the hw_flt output is latched and is reset when vcc is brought low such that v reg < v vreg(uvlo) . 14 pwrgd /pwrgd power good digital output. this output is an open-drain, active-high (pwrgd) or active-low (/pwrgd) signal that should be connected to a +3.3-v logic supply by a 10k ? resistor. this digital output is active after the internal por timer has terminated and becomes asserted when the voltage between the loadsense and the gndsense pins is higher than the controller?s v pgh threshold voltage. it is de-asserted when the voltage between the loadsense and the gndsense pins is less than the controller?s v pgl threshold voltage. 15 i_flt /i_flt load current fault digital output. t his output is an open-drain, active-high (i_flt) or active-low (/i_flt) signal that should be connected to a +3.3v logic supply by a 10k ? resistor. this digital output is active after the internal por timer has terminated and becomes assert ed whenever the primary or secondary overcurrent detection circuits cause the inte rnal circuit breaker to latch off. the digital output remains asserted unless the enable input is toggled high-to- low-to-high as defined by t enlpw or the v cc supply voltage is turned off then on or if the auto-retry mode is enabled. 16 disch discharge external transistor drive output. when enable = low or after a fault condition (either an ov ercurrent fault or hardware fault such as a shorted mosfet) that causes either the primar y and secondary overcurrent detectors to trip the internal circuit break er, the disch circuit is activated to provide gate drive to optional, external transistors (and scr, for very fast load discharge). these transistors serve as auxiliary gat e pull-down or load voltage pull-down switches. a load voltage pull-down is i llustrated in the typical application circuit. 17 gndsense 18 loadsense these input pins (when used together) sense the load voltage and provide feedback to the controller?s adaptiv e va limit and power-good circuits. the voltage across these two pins also sets the controller?s power-is-good status output as defined by the specified v pgh or the v pgl threshold voltages. internal circuit monitors are included if either or both loadsense and gndsense connections are severed or not connected to the load. 19 source external power mosfet source pin monitor. to protect external circuits downstream of the controller, internal monitor circuits are included to sense a shorted drain-source condition of the external power mosfets. 20 cpgnd internal charge pump power ground. conn ect this pin directly to the system?s analog ground plane. 21 gate external n-channel mosfet gate drive output. the gate output signal uses an internal charge pump to charge the gate of an external n-channel mosfet pass transistor.
micrel, inc. mic2310 july 2008 6 m9999-070108-a pin description (continued) pin number pin name pin function 22 sense 23 vccsense by connecting a very low value (m ? ) current sense resistor between these two pins, the mic2310?s internal primary and secondary overcurrent detection circuits monitor the load current. the vccsense pin is the positive (+) input terminal and the sense pin is the negative (-) input terminal of the overcurrent detection circuits. if the voltage across the sense resistor exceeds either the primary overcurrent threshold for a time (t poc ) or the secondary primary overcurrent threshold for any duration, t he mic2310 electronic circuit breaker is tripped, the gate is turned off, the dis ch circuit is activated, and the i_flt digital output is asserted. the controller also incorporates a patent-pending built- in test for shorted current-sense resistors. because of this built-in self test, the mic2310?s electronic circuit breaker ca nnot be disabled by c onnecting together the vccsense and sense pins. 24 vcc positive supply input to the mic2310. t he mic2310 is specified to operate from +10.8v v cc +13.2v and the supply current with enable = high is less than 10ma.
micrel, inc. mic2310 july 2008 7 m9999-070108-a absolute maximum ratings (1) vcc, vccsense, sense, loadsense, enable, cslew, s1, s0, source..................... ?0.3v to +18v gate............................................................. ?0.3v to +30v uvlo, ovp, viss, cretry, cprimary, hw_flt, pwrgd, i_flt, disch, gndsense .... ?0.3v to +6v output current hw_flt, pwrgd, i_flt pi ns ...................................10ma esd rating (all pins) human body model .............................................. 2kv (3) machine m odel ......................................................200v lead temperature (soldering) pb-free package ir reflow ..........................................+260 c +0 c/-5 c storage tem perature..........................?65 c to +150 c operating ratings (2) supply voltage (v cc )................................ +10.8v to +13.2v ambient temperature range (t a ) ................ 0 c to +70 c junction temperature (t j ) ...................................... +125 c package thermal resistance ( ja ) 24-pin t ssop................................................83.8 c/w dc electrical characteristics (4) v cc = +12v, c reg = 0.1f, t a = +25 oc unless otherwise noted. bold indicates specification applies over the full operating temperature range of 0 o c to +70 o c. all voltages are measured with respect to agnd unless otherwise noted. symbol parameter condition min typ max units v cc operating supply voltage (constant output power) 10.8 13.2 v i cc supply current enable = low,high 10 ma v vreg(uvloh) internal vreg undervoltage lockout high threshold voltage v reg low-to-high transition 3.95 4.25 4.5 v v vreg(uvlol) internal v reg undervoltage lockout low threshold voltage 3.70 4.25 v v uvloh uvlo high threshold voltage low-to-high transition 0.96 1.00 1.04 v v uvlol uvlo low threshold voltage high-to-low transition 0.91 0.941 0.97 v i uvlo uvlo pin input current uvlo = 6v 5 a v ovph ovp high threshold voltage low-to-high transition 1.35 1.407 1.45 v v ovpl ovp low threshold voltage high-to-low transition 1.295 1.339 1.395 v i ovp ovp pin input current ovp = 6v 5 a v gspgh ?power-is-good? gate- source threshold (v gate ? v source ) 4.25 5 v v pgh ?power-is-good? high threshold (v loadsense ? v gndsense ) low-to-high transition, (v gate ? v source ) v gspgh measured with respect to gndsense = agnd 9.3 9.7 10.1 v v pgl ?power-not-good? low threshold (v loadsense ? v gndsense ) high-to-low transition, (v gate ? v source ) v gspgh measured with respect to gndsense = agnd 8.4 9 9.6 v v reg v reg output voltage r reg > 1 m ? 4.5 5 5.5 v
micrel, inc. mic2310 july 2008 8 m9999-070108-a symbol parameter condition min typ max units (v loadsense ? v gndsense ) = +12v 54.7 57.2 59.7 mv (v loadsense ? v gndsense ) = +10.8v 60.7 63.5 66.3 mv v cbp primary oc circuit breaker threshold voltage v vccsense ? v sense (v loadsense ? v gndsense ) = +13.2v 49.6 51.9 54.2 mv s[1:0] = l, l 64 75.5 87 mv s[1:0] = l, h 75 87.5 99 mv s[1:0] = h, l 100 116.6 130 mv v cbs secondary oc sense voltage v vccsense - v sense secondary oc detector circuit breaker trips, v loadsense ? v gndsense = 10.8v to 13.2v s[1:0] = h,h 85 102 116 mv i vccsense vccsense pin input current v vccsense = v cc 1 a i sense sense pin input current v sense = v cc 3 a v retryh cretry pin high threshold voltage 1.21 1.25 1.28 v v retryl cretry pin low threshold voltage 0.25 0.3 0.35 v i retryup cretry pin charging current timer on, v retry = 0v -4.25 -3 -1.65 a i retrydn cretry pin pull-down current timer off, v retry = 1.5v 3 ma v pril cprimary pin low threshold voltage during oc response; enable = high; v cc(sense) ? v sense > v cbp measured relative to v reg -1.3 -1.25 -1.2 v enable = high; v cc(sense) ? v sense < v cbp v pril cprimary pin low threshold voltage during shorted c primary detection; measured relative to v reg enable = low -1.3 -1.25 -1.2 v during primary oc fault v cprimary = v reg ; enable = high v cc(sense) ? v sense > v cbp 2.4 3 3.6 a during nominal and reset operation v primary = v reg ? 1.25v; enable = high v cc(sense) ? v sense < v cbp -4.5 -3 -1.5 ma i pri cprimary pin charging current during disable; v cprimary = v reg ? 1.25v enable = low -4.5 -3 -1.5 ma ? v gate gate output voltage (v gate -v cc ): v cc > 10.5v internally clamped 8 15 v ? v cp v cslew ? v sense differential ch arge pump to off 50 mv i slew inrush current slew charging current v cslew = v cc ? 50mv 5 10 15 a
micrel, inc. mic2310 july 2008 9 m9999-070108-a symbol parameter condition min typ max units i gateup gate pin pull-up current charge pump on, v gate = v source = +13.2v -60 -30 -15 a normal gate pin pull-down current enable = low, v gate = 2v 1.0 2.7 4.5 ma i gatedn fault-mode gate pin pull- down current i_flt latched and oc detector trip or in uvlo, v gate = 2v 45 120 ma v gateft(ext) gate-to-agnd fault threshold enable = low 5 v v srcft(ext) source-to-agnd fault threshold enable = low 5 v v thloadsense open loadsense threshold v source - v loadsense 4 v v thgndsense open gndsense threshold v gndsense 4 v en = low, 0v source v cc 18 a en = high, source = v cc 1.5 a i source source pin input current en = high, /fault condition 0v source v cc 18 a +10.8v v loadsense +13.2v 300 a i loadsense loadsense pin input current v loadsense = 0v disch = high 300 a i gndsense gndsense pin input current v gndsense = 0v -400 a ? v ds(fet) shorted r sense threshold voltage at source (v sense ? v source ) v cc(sense) ? v sense = 0v, v gate ? v source > v gspgh 7 mv ? v rsense shorted r sense threshold voltage (v vccsense ? v sense ) v sense ? v source = 30mv, v gate ? v source > v gspgh 12 mv v disch disch pin drive voltage i disch = 12ma 0.4 v i disch disch pin drive current v disch = 2.5v -400 a v iss(lin) linear sensing range v vcc(sense) - v sense 0 90 mv v iss(q) zero voltage viss output voltage v vcc(sense) - v sense = 0mv 7 55 103 mv r viss viss dc output resistance [viss (20 a) -viss (10 a) ]/10 a 100 k ? v iss(sens) viss analog signal sensitivity ? v viss / ? ( v vcc(sense) - v sense ) 28 30 32 v/v e tot viss total error % (240 va) v vcc(sense) - v sense = 60mv 10 %
micrel, inc. mic2310 july 2008 10 m9999-070108-a symbol parameter condition min typ max units e lin viss analog nonlinearity v vcc(sense) - v sense = 0mv to 90mv 6.5 % v ol low-level output voltage i_flt, pwrgd, hw_flt i out = 1.6ma 0.4 v v il low-level input voltage enable, s1, s0 0.8 v v ih high-level input voltage enable, s1, s0 2 v i ih input pull-down current enable, s1, s0 v ih = +0.8v 55 80 120 a notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handling precautions re commended. human body model, 1.5k in series with 100pf. 4. specification for packaged product only. ac electrical characteristics (4) v cc = +12v, c reg = 0.1f, t a = +25 oc unless otherwise noted. bold indicates specification applies over the full operating temperature range of 0 o c to +70 o c. symbol parameter condition min typ max units t por power-on-reset delay v vreg v vreg(uvloh) 6.5 ms t pocsense primary oc detector default response time to gate pin discharge (v vccsense -v sense ) = 70-mv step; primary pin floating; and s[1:0] = h,l c gate = 100pf 200 300 420 s t socsense secondary oc detector response time to gate pin discharge (v vccsense -v sense ) = 200-mv step 0.25 0.5 s t cbreset circuit breaker reset delay time enable low to i_flt low 5 s t enlpw enable low pulse width 200 s t scpdetect shorted c primary detection time to hw_flt latched enable = low or high; 0.25 s t scpdetpor shorted c primary detection delay after primary oc detection v vccsense -v sense v cbp 6.5 ms t dg(fet) mosfet dg short to hw_flt latched enable = low; gateft(ext) asserts hw_flt 10 s t ds(fet) mosfet ds short to hw_flt latched enable = low; srcft(ext) asserts hw_flt 10 s enable = high-to-low after steady-state operation t ds-ssfault 2 mosfet ds short to hw_flt latched enable = high disch = low-to-high 250 s
micrel, inc. mic2310 july 2008 11 m9999-070108-a symbol parameter condition min typ max units t glitch(uvlo) uvlo & ovp glitch filter delay time overdrive = 50mv 10 s t viss(prop) viss propagation delay time v vccsense - v sense = 0mv to 60mv capacitance from viss to gnd is 100pf 7 s t viss(rise) viss rise time v vccsense - v sense = 0mv to 60mv capacitance from viss to gnd is 100pf v viss 10% to 90% 25 s t glitch(pwrgd) pwrgd glitch filter delay time overdrive = 250mv 30 s t dly(disch) gate off to disch delay time 0.25 s notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handling precautions re commended. human body model, 1.5k in series with 100pf. 4. specification for packaged product only.
micrel, inc. mic2310 july 2008 12 m9999-070108-a block diagram
micrel, inc. mic2310 july 2008 13 m9999-070108-a functional description basic startup cycle the basic operation of t he mic2310 is illustrated below in figure 2 from a cold-start condition. with the applied v cc supply low such that the internal v reg voltage is less than the mic2310?s internal v vreg(uvloh) threshold voltage, all state machines are reset, all voltage and current monitor subcircuits are off, and the gate drive circuit is disabled. digital inputs and all open-drain digi tal outputs are inactive. when the applied v cc supply rises such that the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, the t por counter circuit commences. once the timer terminates, all internal state machines are activa ted, the cprimary short detection circuit is on and the dg & ds mosfet short detection circuits are on if enable is low. the i_flt, pwrgd, and hw_flt outputs are valid. upon the application of an enable low-to-high transition after the t por delay, or at the end of the t por delay if enable is already high, a nominal start-up commences where the di d /dt-controlled inrush current (by di d /dt = 17.6x10 -3 i slew / (r sense c slew )) is permitted to exceed the i poc threshold for t poc , until there is sufficient charge stored on the load capacitor as evidenced by the output load voltage profile. note that the secondary overcurrent detection threshold (i soc ) is set externally at t he controller?s s[1:0] pins. once the inrush current exceeds the i soc threshold, the circuit breaker trips without delay and the mic2310 controller shuts down the output. if the inrush current profile does not cause either of the oc detection circuits to trip the circuit breaker and assert the i_flt digital output, the controller will assert the pwrgd digital output when the output load voltage is higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet is higher than the controller?s v gspgh threshold voltage. due to the low r ds(on) of the external mosfet, the output load voltage rises with the gate voltage as the v gs of the mosfet reaches its threshold voltage. once the output load voltage stabilizes near the v cc supply voltage, the v gs of the external mosfet increases above its threshold voltage and eventually exceeds v gspgh . the pwrgd output asserts to signal that the external mosfet is fully enhanced and ready for the application of the full load. v cc enable gate v out i load i_flt pwrgd power good power not good 0a primary & secondary oc detector armed t por i soc = v cbs /r sense set by s[1:0] t poc di d /dt control by c slew i soc i poc i poc = v cbp /r sense +12v, nominal v reg = 5v, nominal peak inrush current = f(c slew , c load ) t poc = f(c primary ) ? t = f(c gate ,v th(fet) ) v gspgh v pgl v vreguvloh v gspgh figure 2. basic startup cycle
micrel, inc. mic2310 july 2008 14 m9999-070108-a primary overcurrent (oc) detector trips circuit breaker and asserts i_flt figure 3 below illustrates the behavior of t he controller to an oc event after the primary and secondary oc detection circuits have been armed (upon the application of an enable low-to-high transition and after t por ) and steady-state operation has been achieved. note that the assertion of the controller?s pwrgd digital output occurs when the output load voltage profile is higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet is higher than the controller?s v gspgh threshold voltage. the use of an external c primary capacitor sets the response time, t poc , of the primary oc detector according to the internal v pril threshold voltage and the cprimary pin discharging current, i pri , where t poc = t pocsense + c primary ? (v pril /i pri ). prior to triggering the primary oc detector (i.e., when v vccsense -v sense < v cbp ), a 3ma current source is enabled to hold the cprimary pin voltage to the internally-generated v reg voltage. when the primary oc detector has been triggered, the 3ma current source is first disabled and a 3a current sink is enabled to discharge the external c primary . when c primary has discharged below v pril , a default timer is enabled. once the default timer (t pocsense ) times out, the circuit breaker is tripped, the 3a current sink is disabled, and the 3ma current source is enabled to discharge c primary back to v reg quickly. concurrently, the gate drive circuit is disabled and a higher current, fault-mode pull-down current sink is enabled at the gate pin. the disch output goes high to (optionally) drive external pull-down circuitry. in the event that the cp rimary pin is left nc (intentionally or otherwise), the overcurrent timer default value is t pocsense (250 s typical), as specified in the ac specification table. once the circuit breaker is latched, the i_flt digital output is asserted and the pwrgd digital output becomes de-asserted when the output voltage profile falls below the controller?s v pgl threshold voltage or the v gs of the external mosfet falls below the controller?s v gspgh threshold voltage. t poc = f(c primary ) v cc enable gate v out v vccsense ?v sense i_flt pwrgd power good power not good 0v primary & secondary oc detectors armed t poc v cbs v cbp i_flt is asserted by primary oc dtector cb trip after t poc +12v, nominal v vreg(uvloh) = +4.25v v reg = 5v, nominal v gspgh v gspgh v pgl t por figure 3. primary oc detector trips circuit breaker
micrel, inc. mic2310 july 2008 15 m9999-070108-a secondary oc detector trips circuit breaker and asserts i_flt figure 4 illustrates the behavi or of the controller to an oc event after the primary and secondary oc detection circuits have been armed (upon the application of an enable low-to-high transition and after t por ) and steady-state operation has been achieved. note that the assertion of the controller?s pwrgd digital output occurs when the output load voltage profile is higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet is higher than the controller?s v gspgh threshold voltage. the controller?s secondary oc detection threshold is set by the status of the cont roller?s s[1:0] pins and its response time is internally set at t socsense as shown in the ac specification table. when the secondary oc detector has sensed a very large current surge (v ccsense ? v sense v cbs ), the circuit breaker is tripped within t socsense . concurrently, the gate drive circuit is disabled and a higher current, fault-mode pull-down current sink is enabled at the gate pin. the disch output goes high to (optionally) drive external pull-down circuitry. once the circuit breaker is latched, the i_flt digital output is asserted and the pwrgd digital output becomes de-asserted when the output voltage profile falls below the controller?s v pgl threshold voltage or the v gs of the external mosfet falls below the controller?s v gspgh threshold voltage. v cc = 12v, nominal v vreg(uvloh) = +4.25v v reg = 5v, nominal figure 4. secondary oc detector trips circuit breaker
micrel, inc. mic2310 july 2008 16 m9999-070108-a charging load by di d /dt ? primary oc trips cb after t poc and cb reset by toggling enable high-to-low figure 5 illustrates the behavi or of the controller to an oc event after the primary and secondary oc detection circuits have been armed (upon the application of an enable low-to-high transition and after t por ). in this example, the load capacitor is charged at a controlled di d /dt rate. steady-state operation is not achieved as the controlled inrush profile causes the primary oc detector to trigger at i poc and continues charging when the t pocsense timer terminates. note that the controller?s pwrgd digital output does not assert because the output load voltage profile at no time rises higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet does not rise higher than the controller?s v gspgh threshold voltage. once the circuit breaker has latched, the i_flt digital output is asserted. when the circuit breaker is tripped by either the primary oc or secondary oc detectors), applying a high-to-low transition on the enable pin will reset the circuit breaker. at a delay defined by t cbreset , the internal circuit breaker is reset and is indicated when the i_flt digital output becomes de- asserted. the earliest a low-to-high transition at enable is permitted to initiate a new start-up sequence is defined by the t enlpw timing specification. v cc = 12v, nominal v vreg(uvloh) = +4.25v v reg = 5v, nominal figure 5. di d /dt load charge profile w/ primary oc circuit breaker (cb) trip w/ cb reset
micrel, inc. mic2310 july 2008 17 m9999-070108-a primary oc trips circui t breaker (cb) and cb resets with c retry (auto-retry timing capacitor) figure 6 illustrates the behav ior of the controller to a primary oc event when a c retry capacitor is used to automatically reset the circuit breaker. the automatic reset operation is the same for the case of a secondary oc event. in this example, the primary and secondary oc detection circuits have been armed (upon the application of an enable low-to-high transition and after t por ) and the load capacitor is charged at a controlled di d /dt rate. note that in this diagram, enable is tied to v cc and rises with v cc . steady-state operation is achieved as the controller?s pwrgd digital output is asserted when the output load voltage profile is higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet is higher than the controller?s v gspgh threshold voltage. when the primary oc detector has been triggered by an output current exceeding i poc for a time t poc , the circuit breaker is tripped, the gate drive circuit is disabled, the fault-mode pull-down current sink is enabled at the gate pin, the disch output goes high, and the i_flt digital output becomes asserted. the use of an external c retry capacitor sets the auto- retry time, t retry , according to the internal v retryh threshold voltage and the cretry pin charging current, i retryup [t retry = c retry * (v retryh /i retryup )]. prior to the tripping of the oc circuit breaker, a 3ma current sink is enabled holding the cretry pin voltage at 0v. when the oc circuit breaker has been tripped, the 3ma current sink is disabled and a 3 a current source is enabled to charge the external c retry capacitor. when c retry has charged above v retryh , the circuit breaker is reset such that the i_flt digital output is de-asserted. additionally, the 3 a current source is disabled and the 3ma current sink is enabled to discharge the cretry pin voltage back to 0v. when c retry has discharged below v retryl , the gate drive circuit is re-enabled and the disch output returns low. for the case of a persistent overcurrent load, the contro ller will continuously cycle between starting up into an oc condition that trips the circuit breaker and the auto-retry time before the circuit breaker is reset.
micrel, inc. mic2310 july 2008 18 m9999-070108-a v cc = 12v, nominal v gspgh v gspgh v pgh v pgl t poc i poc v reg = 5v, nominal t retry t por v cc & vreg enable gate v out i load cretry pwrgd i_flt disch v vreg(uvloh) figure 6. primary overcurrent fault with auto-retry to reset the circuit breaker hw_flt digital output asserted by a mosfet dg short with enable = low in order to protect the system from the result of the installation of a damaged mosfet on the pcb, the controller incorporates a mosfet shorted dg detection scheme whose opera tion is described in figure 7. with the applied v cc supply high such that the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, an elapsed por timer, and with the enable input lo w, a weak current sink at the gate pin attempts to hold the gate voltage at 0v. if there is a dg short on the mosfet, the weak current sink is not capable of holding the voltage at 0v as the gate voltage trac ks the mosfet?s drain voltage. the voltage monitor circuit at the controller?s gate pin will be triggered once the gate voltage crosses the v gateft(ext) threshold voltage. the hw_flt digital output is s ubsequently asserted within a delay approximately equal to the delay in the logic circuits ? no additional timing circuit is required. to clear the latched gate voltage monitor circuit and to reset the hw_flt digital output, the applied v cc supply voltage must fall such that v reg is below the controller?s v vreg(uvlol) threshold voltage.
micrel, inc. mic2310 july 2008 19 m9999-070108-a figure 7. hardware fault detection of a mosfet dg short with enable = low
micrel, inc. mic2310 july 2008 20 m9999-070108-a hw_flt digital output asserted by mosfet ds short with enable = low in order to protect the system from the result of the installation of a damaged mosfet on the pcb, the controller incorporates a mosfet shorted ds detection scheme whose opera tion is described in figure 8. with the applied v cc supply high such that the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, an elapsed por timer, and with the enable input low, a voltage monitor circuit for the controller?s source pin is enabled. if there is a ds short on the mosfet, the external load on the mosfet is not capable of holding the voltage at 0v as the source voltage tracks the mosfet?s drain voltage. the voltage monitor circuit at the controller?s source pin will be triggered once the source voltage crosses the v srcft(ext) threshold voltage. the hw_flt digital output is subsequently asserted within a delay approximately equal to the delay in the logic circuits ? no additional timing circuit is required. to clear the latched source voltage monitor circuit and to reset the hw_flt digital output, the applied v cc supply voltage must fall such that v reg is below the controller?s v vreg(uvlol) threshold voltage. figure 8. hardware fault detection of a mosfet ds short with enable = low
micrel, inc. mic2310 july 2008 21 m9999-070108-a hw_flt asserted by mosfet ds short after steady-state operation then enable = high-to- low figure 9 illustrates the behav ior of the controller to a shorted ds mosfet condition after steady-state operation is achieved via a nom inal start-up. note that the load capacitor at start-up was charged in a controlled di d /dt mode and assertion of the controller?s pwrgd digital output occurs when the output load voltage profile is higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet is higher than the controller?s v gspgh threshold voltage. upon th e application of a high-to- low transition on enable by the service processor, the gate drive circuit is disabled, the weak gate current sink is enabled, the disch output goes high, and the t ds-ssfault timer is started. with the enable input low, a voltage monitor circuit for the controller?s source pin (i.e., v out ) is enabled. if there is a ds short, the voltage at the so urce will not drop to 0v even though the gate is off. if the output voltage at the source pin remains higher than the controller?s v srcft(ext) threshold voltage when the t ds-ssfault timer terminates, the hw_flt digital output is asserted. to repair the damaged mosfet and to reset the hw_flt digital output and t he controller, the service processor instructs the main supply to turn off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage. figure 9. hardware fault by a mosfet ds short after steady-state operation (enable = high-to-low)
micrel, inc. mic2310 july 2008 22 m9999-070108-a hw_flt asserted by mosfet ds short after steady-state operation then a fault condition figure 10 illustrates the behavior of the controller to a shorted ds mosfet condition after steady-state operation is achieved via a nominal start-up. with the occurrence of one of the following fault conditions ? uvlo, ovp, primary oc, secondary oc, open loadsense, or open gnd sense - the gate drive circuit is disabled, the gate fault-mode pull-down current sink is enabled, the disch output goes high, and the t ds-ssfault timer is started. the occurrence of a primary oc fault condition is shown here. the voltage monitor circuit for the controller?s source pin is also enabled. if there is a ds short, the voltage at the source will not drop to 0v even though the gate is off. if the output voltage at the source pin remains higher than the controller?s v srcft(ext) threshold voltage when the t ds-ssfault timer terminates, the hw_flt digital output is asserted. to repair the damaged mosfet and to reset the hw_flt digital output and t he controller, the service processor instructs the main supply to turn off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage. v cc & v reg enable gate v out i load pwrgd i_flt hw_flt disch v vreg(uvlol) v vreg(uvloh) dg short v gspgh v pgh t por t ds-ssfault t por v srcft(ext) t poc v vreg(uvloh) v gspgh v pgl figure 10. hw_flt asserted by a mosfet ds short after steady-state operation then a fault condition
micrel, inc. mic2310 july 2008 23 m9999-070108-a shorted r sense detector trips cb and asserts hw_flt in order to protect the system from the result of the installation of a shorted sense resistor on the pcb, which would increase the effective oc detection thresholds to unsafe levels, the controller incorporates a shorted r sense detection scheme whose operation is described in figure 11. the r sense detection circuitry is enabled upon the application of an enable low- to-high transition, an elapsed por timer, and the v gs of the external mosfet being higher than the controller?s v gspgh threshold voltage. note that for the case of a shorted sense resistor, di d /dt control of the inrush current is disabled and the controller defaults to dv gate /dt control of the gate voltage. an r sense short is detected by comparing the v rs voltage drop across the sense resistor (v ccsense -v sense ) to the v ds voltage drop across the external mosfet (v sense -v source ). to avoid a false r sense short detection at low current, a minimum v ds of ? v ds(fet) must exist across the external mosfet for a shorted sense resistor to be detected. for larger values of v ds across the external mosfet generated by higher load currents, the ? v rsense threshold voltage for the detection of an r sense short follows the equation ? v rsense = 0.5 * (v ds - ? v ds(fet) ). if there exists a short across the s ense resistor such that v rs drops below the ? v rsense threshold voltage, then an internal circuit breaker is tripped, the gate drive circuit is disabled, the gate fault-mode pull-down current sink is enabled, the disch output goes high, and the hw_flt digital output is asserted. to repair the damaged sense resistor and reset the hw_flt digital output, the service pr ocessor instructs the main supply to turn off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage.
micrel, inc. mic2310 july 2008 24 m9999-070108-a v cc & v reg enable gate v out vds(fet) vrs pwrgd hw_flt disch v vreg(uvlol) v vreg(uvloh) v vreg(uvloh) ds(fet) rsense v gspgh v pgh t por t por figure 11. shorted r sense trips circuit break er and asserts hw_flt
micrel, inc. mic2310 july 2008 25 m9999-070108-a shorted c primary detector asserts hw_flt at start-up in order to protect the system from the result of the installation of a shorted or excessively large c primary capacitor on the pcb, the controller incorporates a shorted c primary detection scheme. a shorted cprimary pin or an excessively large c primary capacitor will impact the primary oc detection time, t poc. the operation of the shorted c primary detection scheme at start-up is described in figure 12. prior to power-up, the cprimary pin is discharged to 0v. as the applied v cc supply and the internal v reg voltage rise, a 3ma current source is applied to the cprimary pin to charge c primary to v reg . when the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, the t por timer is initiated. for the case of a reasonable c primary capacitor value, one which keeps the primary oc response time, t poc , less than ? 0.5s, c primary charges above v prih before the por timer terminates and normal operation commences. however, if the cprimary pin is shorted to gnd or c primary is too large, as in this timing diagram, the por timer terminates before c primary charges above v prih and a shorted c primary is detected. when a c primary short is detected, the gate drive circuit and the disch output are not affected, howe ver, the hw_flt digital output is asserted. to repair the damaged c primary capacitor and reset the hw_flt digital output, the service processor instructs the main supply to turn off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage. v cc & v reg enable gate v out i load pwrgd cprimary hw_flt disch v vreg(uvlol) v vreg(uvloh) v vreg(uvloh) v gspgh v pgh v gspgh t por v prih cprimary too large v prih t por smaller cprimary v pgl figure 12. shorted c primary detector asserts hw_flt at start-up
micrel, inc. mic2310 july 2008 26 m9999-070108-a shorted c primary detector asserts hw_flt during steady-state figure 13 illustrates the behavior of the controller to a shorted c primary capacitor condition after steady-state operation is achieved via a nominal start-up. if a c primary short occurs during steady-state operation, the cprimary pin voltage will drop below the v pril threshold voltage and a shorted c primary is detected. when a c primary short is detected, the gate drive circuit remains enabled and the disch output remains low such that the external mosfet remains on, however, the hw_flt di gital output is asserted. to repair the damaged c primary capacitor and reset the hw_flt digital output, the service processor instructs the main supply to turn off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage. v cc & v reg enable gate v out i load pwrgd cprimary disch hw_flt v vreg(uvlol) v vreg(uvloh) v vreg(uvloh) v gspgh v gspgh t por v prih shorted cprimary v pril cprimary repaired t por v prih v pgl v pgh figure 13. shorted c primary detector asserts hw_flt during steady-state
micrel, inc. mic2310 july 2008 27 m9999-070108-a shorted c primary detector asserts hw_flt after primary oc event the diagram in figure 14 illustrates the behavior of the controller to a shorted c primary capacitor condition after steady-state operation is achieved via a nominal start-up and after a primary oc event has occurred. as described previously, during a primary oc event, the c primary capacitor is discharged as part of setting the primary oc detector response time, t poc . in order to prevent a false c primary short detection from occurring while the cprimary pin is being intentionally discharged, the c primary short detection circuit is disabled when the primary oc detector detects an overcurrent. in addition, the c primary short detection circuit is not re-enabled until after a time delay, t scpdetpor , once the primary oc detector no longer detects an overcurrent. this delay time should allow a capacitor of reasonable size to be charged back up above v prih , even if it has been discharged to 0v, such that a false c primary short is not indicated when the c primary short detection circuitry is re- enabled. in the timing diagram, c primary becomes shorted during the primary oc event. when the cprimary pin voltage falls below v pril , the t pocsense timer is enabled. once this timer times out, the circuit breaker is tripped, i_flt is asserted, the gate drive circuitry is disabled, the gate fault-mode pull-down current sink is enabled, and the disch output goes high. as the external mosfet is turned off, the output current drops and an overcurrent condition is no longer detected. this initiates the t scpdetpor timer. since c primary does not charge back up above v prih before this timer expires, hw_flt is asserted after the t scpdetpor time. to repair the damaged c primary capacitor and reset the hw_flt digital output, the service processor instructs the main supply to turn off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage.
micrel, inc. mic2310 july 2008 28 m9999-070108-a v cc & v reg enable gate v out i load pwrgd cprimary hw_flt disch i_flt v vreg(uvloh) v vreg(uvloh) v vreg(uvlol) v gspgh v pgh i poc t por v prih t poc v pril cprimary repaired v prih t scpdetpor t por t pocsense v gspgh shorted cprimary figure 14. shorted c primary detector asserts hw_flt after primary oc event
micrel, inc. mic2310 july 2008 29 m9999-070108-a open loadsense detector trips cb in order to protect the system from the result of an open loadsense pin, the controller incorporates an open loadsense detection scheme. an open loadsense pin could result in the effective primary oc detection threshold being at an unsafe level. the timing diagram in figure 15 describes the operation of this function. with the applied v cc supply high such that the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, an elapsed por timer, and with the application of an enable low-to-high transition, the gate drive circuitry is enabled and the gate voltage begins to rise. as the external mosfet turns on, the source voltage begins to rise also. normally, the loadsense voltage would rise with the source voltage. however, if the loadsense pin is open, the loadsense voltage will remain at a lower voltage due to the load of other internal circuitry. an open loadsense pin is detected by comparing the voltage at the source pin to the voltage at the loadsense pin. once the voltage at the source pin di ffers from the voltage at the loadsense pin by v thloadsense , a circuit breaker is tripped, the gate drive circuitry is disabled, the gate fault-mode pull-down current sink is enabled, and the disch ou tput goes high. this circuit breaker can be reset, such that the gate drive circuitry can be re-enabled, by either a high-to-low transition on enable or turning off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage. v cc & v reg enable gate v out i load pwrgd loadsense disch v vreg(uvlol) v gspgh v pgh t por v vreg(uvloh) v thloadsense loadsense open v vreg(uvloh) loadsense connected t por figure 15. open loadsense detector trips cb
micrel, inc. mic2310 july 2008 30 m9999-070108-a open gndsense detector trips cb in order to protect the system from the result of an open gndsense pin, the controller incorporates an open gndsense detection scheme. an open gndsense pin could result in the effective primary oc detection threshold being at an unsafe level. the timing diagram in figure 16 describes the operation of this function. with the applied v cc supply high such that the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, an elapsed por timer, and with the application of an enable low-to-high transition, the gate drive circuitry is enabled and the gate voltage begins to rise. as the external mosfet turns on, the source voltage begins to rise also and the loadsense voltage follows the source voltage. normally, the gndsense pin would remain at 0v. however, if the gndsense pin is open, the gndsense volt age will rise due to the load of other internal circuitry. an open gndsense pin is detected by comparing the voltage at the gndsense pin to the voltage at the agnd pin. once the voltage at the gndsense pin differs from the voltage at the agnd pin by v thgndsense , a circuit breaker is tripped, the gate drive circuitry is disabled, the gate fault-mode pull-down current sink is enabled, and the disch ou tput goes high. this circuit breaker can be reset, such that the gate drive circuitry can be re-enabled, by either a high-to-low transition on enable or turning off the v cc supply voltage to the controller such that v reg falls below the controller?s v vreg(uvlol) threshold voltage. v cc & v reg enable gate v out i load pwrgd gndsense disch v vreg(uvlol) v gspgh v pgh t por v vreg(uvloh) v thgndsense v vreg(uvloh) gndsense connected t por gndsense open figure 16. open gndsense detector trips cb
micrel, inc. mic2310 july 2008 31 m9999-070108-a uvlo and ovp operation the system can be protected against an under- voltage condition or an over-voltage condition on the v cc supply by using an external resistor divider and the uvlo and ovp pins, respectively. figure 17 illustrates the timing of t he gate and digital pin outputs when the input supply crosses the uvlo and ovp thresholds. when the voltage applied to the uvlo pin is less than the v uvlol threshold voltage or the voltage applied to the o vp pin is greater than the v ovph threshold voltage, the gate drive circuitry is disabled, the gate fault-mode pull-down current sink is enabled, and the disch output goes high. increasing v cc such that the voltage applied to the uvlo pin increases above v uvloh or decreasing v cc such that the voltage applied to the ovp decreases below v ovpl re-enables the gate drive circuit and forces the disch output low, allowing the controller to return to normal operation. v cc & v reg enable gate v out i load pwrgd ovp uvlo disch v vreg(uvloh) v gspgh v pgh uvlol v pgl uvloh ovph ovpl v gspgh v pgh v pgl v pgh v gspgh t por figure 17. uvlo and ovp operation
micrel, inc. mic2310 july 2008 32 m9999-070108-a viss output operation the viss output provides a voltage which is proportional to the output current flowing in the external sense resistor. figure 18 illustrates the operation of this output. with the applied v cc supply high such that the internal v reg voltage is above the controller?s v vreg(uvloh) threshold voltage, an elapsed por timer, and with the application of an enable low-to-high transition, the gate drive circuitry is enabled. when the output load voltage profile is higher than the controller?s v pgh threshold voltage and the v gs of the external mosfet is higher than the controller?s v gspgh threshold voltage, the pwrgd digital output is asserted and the viss output becomes active. the current flowing in the external sense resistor is determined by sensing the voltage across the sense resistor (v ccsense -v sense ). as the output current varies under changing load conditions, v ccsense -v sense also varies and the viss output voltage changes proportionally according to v iss(sens) . when the external mosfet is disabled, either by a high-to-low transition on enable or due to a fault condition, the v gs of the external mosfet falls below the controller?s v gspgh threshold voltage. this causes the pwrgd digital output to be de-asserted and the viss output to be disabled. v cc & v reg enable gate v out i load pwrgd viss disch v vreg(uvloh) v vreg(uvlol) v gspgh v pgh v gspgh v pgl t por figure 18. viss operation
micrel, inc. mic2310 july 2008 33 m9999-070108-a applications information the mic2310 can be configured to address power- limiting applications other than the 240-va power control (ul60950 safe power handling systems). there are two key requirements to consider in selecting the external components for use in various power-limit applications: 1) the value (and tolerance) of the r sense current sensing resistor; and 2) the r ds(on) of the external power mosfet. these two components are vital with regards to the shorted r sense detection scheme such that the values of each need to be chosen such that variations in r ds(on) and r sense over process, supply, and temperature does not result in a false r sense short detection. in short, the value of r ds(on) of the external mosfet should be selected to not exceed twice the value of r sense over process, supply, and temperature, to avoid the generation of a false r sense short detection.
micrel, inc. mic2310 july 2008 34 m9999-070108-a package information 24-pin tssop (ts) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life suppo rt devices or systems are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2008 micrel, incorporated.

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